Hello Everybody,
Long time no see... :)
I find that I'm losing to follow what everybody did since the blog are not up-to-date. However, I'd give a brief introduction of the SoC system adopted here. I especially highlight its debugging utility, being treated as a reference of 8051 project.
The SoC system is provided by AreoFlex. It consists of IP cores, OSs, compilers, debugger and simulators. Most are open-source following GPL licensing and some are commercial. The Leon3 is the processor core using the SPARC V8 architecture. The SoC system contains AMBA bus with plug&play functionality, so modules connect to the bus. Essential IPs are built in the package, as shown in the figure below. This system doesn't bound to any boards or processes. It means you can use it on whether Xilinx/altera FPGA and ASIC design. However, they collect various FPGA boards and fit the SoC system on them, including the peripherals on the board. A tool to configure the IPs is included. It helps you to construct the system you want, even without modifying any codes. You also can build multi-core system by configuring.
After configuring, synthesizing, and programming onto FPGA, you can execute program on the LEON3 processor. The GrMon is provided as a debugger. It can obtain the information from processors and other AHB slave by using the debug link module, which is a AHB master, as shown above. However, to access the registers in the processor, an additional debug support unit (DSU) is designed. The DSU is a separate AHB slave module, accessing the processor only when the processor is in debug mode. Once the GrMon tends to access the status of processor, its corresponding debug link module will signal the DSU. The DSU will enforce the processor to enter debug mode and halt, so that DSU can work. A DSU can cope with up to 16 processors.
As mentioned above, the SoC system has no limitation to FPGA boards, so their debugging environment is adaptable by providing various debug link modules. For example, it supports Xilinx standard USB-JTAG download cable for debugging. Some may question if there is no interface for the existing debug link. Don't worry. If you can connect your FPGA board with PC, all you need to do are to design your own debug link master module connecting to PC with interface on the board and to enable GRMon control your hardware module by implementing a set of pre-defined callback functions being invoked by GRMon. This makes it possible to build the system on the existing FPGA boards in our lab. :p
Moreover, the GRMon is an Eclipse plug-in and can attach with GDB for debugging. More information here.
Okay, that's it!
