2008_10_29在MATLAB的演講: Electronic System Level Simulation/Verification in Heterogeneous Environment Using MATLAB/Simulink and FPGA

演講的題目主要是實驗室中所做的把SystemC, FPGA與Matlab/Simulink合起來 一起進行simulation. 我們用很簡單的JPEG encoder來當例子. JPEG的source code是網路上下載的open source. 經過簡單的修改後嵌入到SystemC模組裡, 並且把DCT搬到外面來, 如此可以驗證在三個不同的DCT實做是否一致. 以FPGA來代替一般的HDL Simulato, 速度當然很快.

感謝巴菲特與DNA的協助, 這個demo很成功. 下面是demo的snapshot. webcam對著aaa的背景, 然後用上面的工具壓一張JPEG影像.

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當天有一百多人來聽, 演講後也有約7,8人來問, 其中還有Sunplus Core的技術副總監, 因為時間有限而且我知道他們的DSP是跟工研院STC技轉來的, 所以我跟他說以後我們會跟STC合作, 以後三方可以就此一議題來合作.

題目與摘要如下:

Electronic System Level Simulation/Verification in Heterogeneous Environment Using MATLAB/Simulink and FPGA

Abstract

Electronic System Level (ESL) design has become the most popular methodology for designing highly complex VLSI systems such as SoC. Instead of working on implementation details, transaction level modeling (TLM) has been considered a powerful method to speed up design process by building a reference model on which hardware and software development can be based. Currently, SystemC2.2 and TLM2.0 library have become IEEE/OSCI standard tools.

However, since modules/parts in a system may be developed separately using different tools in different design stages at different speeds of progress, it is necessary to be able to simulate and verify the system in such a heterogeneous environment. In this talk, system level simulation incorporating SystemC/TLM, MATLAB/Simulink and FPGA is presented. MATLAB which is usually used for algorithm development may sit at the highest abstraction level while FPGA which is used in emulation usually sits at the much lower abstraction level. Hence, simulation/verification across different abstraction levels can be achieved. The consistency of a module designed in different abstraction levels can be maintained. As such, functionality correctness of system can be improved.

投影片在此:

System Level Design/Simulation/Verification Using MATLAB/Simulink and FPGA

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